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LanceSoft, Inc. is looking for a Design Verification Engineer who will be responsible for IP level ASIC verification, debugging firmware and RTL code using simulation tools, and developing UVM based verification frameworks and testbenches. The ideal candidate should have a Master's degree with 5 years of experience or a Bachelor's degree with 8 years of experience, and be proficient in using UVM testbenches in both Linux and Windows environments. A solid understanding of Verilog, System Verilog, C, and C++ is essential, along with scripting language experience in Perl, Ruby, Makefile, and shell. This position offers a pay rate of $85/hr to $95/hr on W2.