Design Verification Engineer
- Published on
About the Role
LanceSoft, Inc. is looking for a Design Verification Engineer who will focus on IP level ASIC verification. The candidate will be responsible for debugging firmware and RTL code using simulation tools and developing UVM-based verification frameworks along with testbenches, processes, and flows. Strong knowledge of UVM concepts and hands-on experience with the SystemVerilog language is imperative.
About the Candidate
Expectations:
- Ideally holds a Master’s degree with 5 years of relevant experience or a Bachelor’s degree with 8 years of relevant experience.
- Proficient in debugging firmware and RTL code.
- Experienced in using UVM testbenches and comfortable in both Linux and Windows environments.
Nice to Have Skills:
- Familiarity with scripting languages such as Perl, Ruby, Makefile, and shell.
- Experience in automating workflows in a distributed compute environment.
About the Company
LanceSoft, Inc. is an established firm specializing in technology solutions, providing innovative strategies to enhance performance across the tech industry. With a culture of excellence and teamwork, they empower their engineers to grow and lead in their respective fields.
Company Culture and Benefits
LanceSoft values collaboration, innovation, and professional development, offering competitive pay rates of $85/hr to $95/hr on W2. The organization emphasizes a supportive work environment where ideas can flourish and contributions are recognized. Remote working flexibility is included to support a healthy work-life balance.
Employment Type
This role is a full-time position with a focus on fostering a dynamic and inclusive work culture.